The PCI Express Architecture

ABSTRACT

Today, computing industry is demanding for improved performance in terms of faster data transfer and increased processing speeds. As the demand for richer application content continues to scale, so must the hardware and processing required to support it. Introduction of high performance processors and high speed memory, have alleviated the bottlenecks in the field to a certain extent. But the I/O interconnect and graphics platform remains the same with PCI and AGP, whose further enhancement introduce complexity and increased cost. Thus a new generation I/O interconnect is essential. The PCI Express ^TM (Formerly 3GIO) is the next generation chip-to-chip and chip-to-adaptor interconnect with improved bandwidth and low latency. PCI Express provides a scalable, high speed, point-to-point serial I/O bus that maintains backward compatibility with PCI applications and drivers. PCI Express is a breakthrough for server, desktop and notebook platforms and has significant positive impacts for networking. It offers high bandwidth with lower pin counts and allows additional scaling in performance. With its increased performance and scalability, it seems inevitable that PCI Express I/O system will be the basis for computers for many years to come.